1. Field of the Invention
This invention relates to the field of integrated capacitors.
2. Description of the Related Art
Integrated circuits (ICs), particularly those which implement analog circuitry, often have a need for a capacitance element. Such capacitances provide many different circuit functions, such as filtering and compensation.
Traditional analog IC processes construct capacitors by sandwiching a dielectric layer between conductors. For example, a polysilicon layer deposited over a silicon substrate can serve as a capacitor's plates, with an oxide layer between the plates serving as a dielectric layer. Oxide layers are very thin, and hence this type of structure has a very high specific capacitance. Unfortunately, the polysilicon layers and terminals deposited thereon form a MOS structure. This leads to a highly non-linear capacitor unless a large DC bias is maintained across the capacitor. Such biases are incompatible with the low power supply voltages used with modern circuits. Further, MOS capacitors are polarized, and therefore cannot be used in circuits such as switched-capacitor circuits in which the terminals of the capacitor are flipped in polarity.
Capacitors may also be constructed using an IC's metal interconnect layers, with a dielectric layer between the metal layers to form a metal—metal capacitor. While such capacitors avoid the problems discussed above with respect to MOS capacitors, metal—metal capacitors have two drawbacks of their own. The interlayer dielectrics are relatively thick; hence, metal—metal capacitors have relatively low specific capacitances. Second, such capacitors suffer from parasitic, or “back-plate” capacitance between one, or both, of the terminals and the substrate of the IC. In most processes, the dielectric thickness between the interconnect layers is roughly equal to the dielectric thickness between the substrate and the bottom interconnect layer. Hence, the parasitic capacitance is roughly equal to the active capacitance.
IC processes having three metal interconnect layers have become common. In such processes, a stacked plate structure can be used to provide an improved capacitor structure over the metal—metal structure described above. In this case, the capacitor has two dielectric layers sandwiched between the three metal layers. The outer metal layers are electrically connected to form one terminal of the capacitor, while the middle layer forms the other terminal. This doubles the specific capacitance while leaving the parasitic capacitance approximately the same. Hence, such structures have roughly a 2:1 active to parasitic capacitance ratio.
Other stacked plate approaches are described, for example, in U.S. Pat. No. 5,208,725 to Akcasu, U.S. Pat. No. 5,978,206 to Nishimura et al., and U.S. Pat. No. 6,178,083 to Appeltans et al. Each of these devices relies on structures of parallel or orthogonal conductors which contribute to the device's total capacitance. However, special processing steps are typically required to implement these devices.